Huawei’s semiconductor chief He Tingbo introduced what the company calls “Tau Scaling” at the IEEE International Symposium on Circuits and Systems in Shanghai on May 25, saying high-end chips could reach transistor density equivalent to a 1.4-nanometer process by 2031.

Huawei did not announce mass production of a 1.4nm manufacturing process. It gave no fab plan, lithography detail, yield data or cost curve. The claim is about equivalent transistor density, with the work centered on chip design, circuit layout and system communication.

Huawei semiconductor chief He Tingbo speaking at ISCAS 2026 in Shanghai
Huawei semiconductor chief He Tingbo spoke at ISCAS 2026 in Shanghai on May 25. Image source: Huawei.

Reuters kept the word “equivalent” in its report and noted that Huawei did not provide independent performance data. The South China Morning Post used the same framing. A manufacturing-node announcement usually comes with production timing, process details and yield clues. Huawei has not provided those.

Mass Production Is Still Far Away

When TSMC, Samsung or Intel talks about 1.4nm, investors ask about transistor architecture, EUV layers, materials, yield and production schedules. Huawei’s presentation did not go there.

He described “time scaling”: lowering the circuit time constant τ, shortening signal delays, and using LogicFolding to reduce critical paths. The argument moves away from simply shrinking line widths and puts more weight on design and system communication.

What Can Be Checked

τ is not new physics

RC delay, critical paths and interconnect load are familiar chip-design problems. Huawei has put them under a new label: time scaling.

The “law” is Huawei’s name

Moore’s Law came from long-running industry data. Tau Scaling has just been proposed and has not yet been tested at that level.

The 381-chip figure needs detail

Huawei says it has designed and mass-produced 381 chips in six years, but it did not break them down by category, process node, volume or LogicFolding usage.

The next Kirin will be dissected

Huawei says a new Kirin chip due in autumn 2026 will use LogicFolding. Teardowns will focus on die area, power draw, heat and sustained performance.

Signal Delay Is the Point

Longer wires, higher resistance and more capacitance slow a chip down. As transistors keep shrinking, interconnects, data movement and system communication have become harder to ignore.

Huawei’s list includes reducing device resistance and parasitic capacitance, shortening critical paths, designing software and chip architecture together, and using its Lingqu bus to cut system-level communication delays. Each of those has a recognizable counterpart in existing chip design.

TSMC, Nvidia, Apple and AMD all deal with similar problems: move data closer, make communication faster and keep power lower. Huawei is grouping that kind of engineering work under “time scaling” and presenting it as its own answer.

Lithography Remains the Constraint

US export controls still restrict China’s access to advanced lithography equipment, some EDA tools, leading-edge manufacturing and high-end AI chips. Huawei can move more performance work into design, but manufacturing pressure has not gone away.

Shorter routing, more parallelism and lower communication delay can make a chip perform better on the same process. Manufacturing still determines transistor size, leakage, frequency headroom, yield and cost. Design can narrow part of the gap; it cannot replace the fab.

“Equivalent density” may come from layout and circuit organization. It does not automatically mean equal power consumption, equal yield, equal cost, or equal performance across every workload.

The autumn Kirin chip should leave comparable evidence: die size, sustained performance, power draw, heat and teardown findings. Tau Scaling will have to show up in product data, not just in conference language.

From Concept to Product

Huawei has pointed to the next Kirin chip as the first public sample. A phone chip leaves evidence that can be compared: benchmarks, battery life, heat, modem performance, on-device AI and foundry clues.

Peak scores will not be enough. If LogicFolding shortens critical paths, sustained workloads should show lower power draw, less thermal throttling or steadier performance at similar power.

The 381-chip number also needs to be read inside Huawei’s business. Telecom gear, smartphones, servers, cars, energy equipment and industrial devices use very different chips. A headline total shows organization and volume; it does not by itself prove that Huawei’s top-end logic chips are near the global frontier.

Chinese Stocks Moved First

Chinese semiconductor shares rose on May 25, with the STAR Market and parts of the chip supply chain drawing fresh buying. Traders were buying the Huawei supply-chain story, domestic substitution and AI-computing demand, not an overnight change in wafer manufacturing.

The near-term watchlist is more practical: design tools, advanced packaging, high-speed interconnects, servers, cooling, power management and domestic EDA. If the next Kirin produces a better power-efficiency curve, Huawei-linked names will get a new valuation argument. If the improvement is modest, the trade will fall back to handset sales, AI-server shipments and real orders.

The next answers will come from hardware. A Kirin chip that only raises peak benchmark scores will not settle the matter. A chip that improves sustained performance, power and heat together would give Huawei’s claim more weight. AI-server chips and supply-chain orders will matter just as much.

Sources: Huawei May 25 statement, Reuters, South China Morning Post, Beijing News Shell Finance, People’s Daily Online and Science and Technology Daily. This article is not investment advice.